1. Field
This disclosure relates generally to analog-to-digital converters, and more specifically, to an analog-to-digital converter (ADC) having a comparator for a multi-stage sampling circuit and method therefor.
2. Related Art
A redundant signed digit (RSD) algorithm is used in a cyclic, or pipelined, ADC. The RSD ADC typically converts an analog signal to a corresponding digital value through a series of sample and comparison phases using sampling circuits and corresponding sets of comparators. The sampling circuit may include a number of capacitors and switches to sample an analog input signal to be converted to a digital form. A resolution of the RSD ADC may depend on the number of capacitors in each sampling circuit and the number of comparators in a set of comparators. Typically, in a RSD stage, a single set of comparators is used with each sampling network. However, in a double-sampled RSD stage, for example, using two sets of comparators requires a large amount of surface area on an integrated circuit. To reduce the surface area required for the ADC, only one set of comparators may be used and shared between two sampling circuits. The use of the single set of comparators may require that a sampling clock be provided at two times a clock rate used for an ADC having two sets of comparators. Also, when a comparator is activated, or tripped, to perform the comparison, the comparator operation may affect the stored charge on the sampling capacitors, thus reducing the accuracy of a conversion.
Therefore, what is needed is an RSD ADC that solves the above problems.